Archipelago: A polymorphic cache design for enabling robust near-threshold operation

Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely used technique to tackle this problem when high performance is not the main concern. However, the minimum achievable supply voltage for the processor is often bounded by the large on-chip caches since SRAM cells fail at a significantly faster rate than logic cells when reducing supply voltage. This is mainly due to the higher susceptibility of the SRAM structures to process-induced parameter variations. In this work, we propose a highly flexible fault-tolerant cache design, Archipelago, that by reconfiguring its internal organization can efficiently tolerate the large number of SRAM failures that arise when operating in the near-threshold region. Archipelago partitions the cache to multiple autonomous islands with various sizes which can operate correctly without borrowing redundancy from each other. Our co...

• Type: Journal
• Year: 2011
• Where: HPCA
• Authors: Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke
• Keywords: Distributed And Parallel Computing, HPCA 2011, Power Savings, Supply Voltage, Voltage