66 search results - page 4 / 14 » ae 2005 |
CHES
2005
Springer
14 years 3 months ago
2005
Springer
A key step in the Advanced Encryption Standard (AES) algorithm is the “S-box.” Many implementations of AES have been proposed, for various goals, that effect the S-box in vari...
CHES
2005
Springer
14 years 3 months ago
2005
Springer
Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3...
GLVLSI
2005
IEEE
14 years 3 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
INDOCRYPT
2010
Springer
13 years 7 months ago
2010
Springer
In the recent years, Higher-order Side Channel attacks have been widely investigated. In particular, 2nd-order DPA have been improved and successfully applied to break several mask...
ISPEC
2011
Springer
13 years 21 days ago
2011
Springer
The AES block cipher has a 128-bit block length and a user key of 128, 192 or 256 bits, released by NIST for data encryption in the USA; it became an ISO international standard in ...