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APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-proce...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
—The Massey-Omura multiplier is a well-known sequential multiplier over finite fields GF(2m ), which can perform multiplication in m clock cycles for the normal basis. In this ar...
APCCAS
2006
IEEE
13 years 9 months ago
2006
IEEE
The paper presents a hardware friendly fast algorithm and its architecture for motion estimation (ME) in H.264 video coding. The fast algorithm adopts the quarter pel subsampling a...
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APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
—A method of embedding data in a JPEG color image for applications such as authentication of an employee carrying a picture identification card is described. Embedding of data, s...