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ASPDAC
1999
ACM
101views Hardware» more  ASPDAC 1999»
14 years 2 months ago
Optimal Evaluation Clocking of Self-Resetting Domino Pipelines
We describe a high performance clocking methodology for domino pipelines. Our technique maximizes the clock rate of the circular pipeline (“ring”) while maintaining the ring c...
Kenneth Y. Yun, Ayoob E. Dooply
ASPDAC
1999
ACM
144views Hardware» more  ASPDAC 1999»
14 years 2 months ago
Model Order Reduction of Large Circuits Using Balanced Truncation
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...
Payam Rabiei, Massoud Pedram
ASPDAC
1999
ACM
101views Hardware» more  ASPDAC 1999»
14 years 2 months ago
Fast Boolean Matching Under Permutation Using Representative
—This paper presents an efficient method to check the equivalence of two Boolean functions under permutation of the variables. The problem is also known as Boolean matching. As ...
Debatosh Debnath, Tsutomu Sasao
ASPDAC
1999
ACM
157views Hardware» more  ASPDAC 1999»
14 years 2 months ago
A Genetic Algorithm based Approach for Multi-Objective Data-Flow Graph Optimization
: This paper presents a genetic algorithm based approach for algebraic optimization of behavioral system specifications. We introduce a chromosomal representation of data-flow gr...
Birger Landwehr
ASPDAC
1999
ACM
149views Hardware» more  ASPDAC 1999»
14 years 2 months ago
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The B...
Jinsong Hou, Zeyi Wang, Xianlong Hong