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ASPDAC
2006
ACM
158views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Process-induced skew reduction in nominal zero-skew clock trees
— This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis framewor...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A fast logic simulator using a look up table cascade emulator
— This paper shows a new type of a cycle-based logic simulation method using a Look-Up Table (LUT) cascade emulator. The method first transforms a given circuit into LUT cascade...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
ASPDAC
2006
ACM
92views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Optimization of circuit trajectories: an auxiliary network approach
—On optimizing circuit trajectories, i.e. continuous paths of circuit parameters, the paper presents an auxiliary network approach, which utilizes Pontryagin’s Minimum Principl...
Baohua Wang, Pinaki Mazumder
ASPDAC
2006
ACM
119views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A dynamic test compaction procedure for high-quality path delay testing
- We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set...
Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, T...
ASPDAC
2006
ACM
103views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Prefetching-aware cache line turnoff for saving leakage energy
Abstract— While numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This paper studies this i...
Ismail Kadayif, Mahmut T. Kandemir, Feihui Li