— This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis framewor...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
— This paper shows a new type of a cycle-based logic simulation method using a Look-Up Table (LUT) cascade emulator. The method first transforms a given circuit into LUT cascade...
—On optimizing circuit trajectories, i.e. continuous paths of circuit parameters, the paper presents an auxiliary network approach, which utilizes Pontryagin’s Minimum Principl...
- We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set...
Abstract— While numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This paper studies this i...