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ASPDAC
2006
ACM
288views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Algorithms and DSP implementation of H.264/AVC
Abstract - This survey paper intends to provide a comprehensive coverage of the techniques that are pertinent to the processor-based implementation of H.264/AVC video codec, partic...
Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-...
ASPDAC
2006
ACM
120views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Design space exploration for minimizing multi-project wafer production cost
- Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper1 , we propose a methodology to explore reticle floopla...
Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-...
ASPDAC
2006
ACM
117views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A memory grouping method for sharing memory BIST logic
- With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST lo...
Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
ASPDAC
2006
ACM
99views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method
— This paper presents an architecture and a synthesis method for programmable numerical function generators (NFGs) for trigonometric, logarithmic, square root, and reciprocal fun...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
14 years 1 months ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...