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ASPDAC
2006
ACM
129views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)
With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged...
Vineet Agarwal, Janet Meiling Wang
ASPDAC
2006
ACM
141views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Depth-driven verification of simultaneous interfaces
The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This t...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
ASPDAC
2006
ACM
98views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Timing-driven placement based on monotone cell ordering constraints
− In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed th...
Chanseok Hwang, Massoud Pedram
ASPDAC
2006
ACM
137views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Parameterized block-based non-gaussian statistical gate timing analysis
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
ASPDAC
2006
ACM
88views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation
— A substrate-coupling equivalent circuit can be derived for an arbitrary guard ring test structure by way of F-matrix computation. The derived netlist represents a unified impe...
Daisuke Kosaka, Makoto Nagata