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ASPDAC
2008
ACM
106views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and Krylov subspace projection-based model order re...
Duo Li, Sheldon X.-D. Tan
ASPDAC
2008
ACM
108views Hardware» more  ASPDAC 2008»
13 years 11 months ago
A new global router for modern designs
- In this paper, we present a new global router, NTHU-Route, for modern designs. NTHU-Route is based on iterative rip-ups and reroutes, and several techniques are proposed to enhan...
Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang
ASPDAC
2008
ACM
83views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Run-time power gating of on-chip routers using look-ahead routing
Since on-chip routers in Network-on-Chips play a key role in on-chip communication between cores, they should be always preparing for packet injections even if a part of cores are ...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
ASPDAC
2008
ACM
169views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Buffered clock tree synthesis for 3D ICs under thermal variations
In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides...
Jacob R. Minz, Xin Zhao, Sung Kyu Lim
ASPDAC
2008
ACM
90views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Vertical via design techniques for multi-layered P/G networks
- In multi-layered power/ground (P/G) networks, to connect the whole network together, vertical vias are usually placed at intersections between metal wires of adjoining layers. In...
Shuai Li, Jin Shi, Yici Cai, Xianlong Hong