Sciweavers

80 search results - page 16 / 16
» aspdac 2010
Sort
View
ASPDAC
2010
ACM
112views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
Abstract-- Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused d...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
13 years 9 months ago
A dual-MST approach for clock network synthesis
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangel...
ASPDAC
2010
ACM
155views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Efficient model reduction of interconnects via double gramians approximation
The gramian approximation methods have been proposed recently to overcome the high computing costs of classical balanced truncation based reduction methods. But those methods typi...
Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yic...
ASPDAC
2010
ACM
120views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method
In this paper, we propose a new wideband model order reduction method for interconnect circuits by using a novel adaptive sampling and error estimation scheme. We try to address t...
Hai Wang, Sheldon X.-D. Tan, Gengsheng Chen
ASPDAC
2010
ACM
637views Hardware» more  ASPDAC 2010»
13 years 9 months ago
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography
As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this pape...
Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, D...