We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power densi...
Salvatore Carta, Andrea Acquaviva, Pablo Garcia De...
— Zadeh proposed the paradigm of computing with words (CWW). We have proposed a CWW architecture for making subjective judgments, called a Perceptual Computer (PerC). Because wor...
This paper presents a scalable, adaptive and timebounded general approach to assure reliable, real-time Node-Failure Detection (NFD) for large-scale, high load networks comprised ...
Matthew Gillen, Kurt Rohloff, Prakash Manghwani, R...
: This paper provides a methodology to characterize the accuracy of PMU data (GPS-synchronized) and the applicability of this data for monitoring system stability via visualization...
George J. Cokkinides, A. P. Sakis Meliopoulos, Geo...