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ESTIMEDIA
2009
Springer
13 years 5 months ago
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications
The increasing demand for low power and high performance multimedia embedded systems has motivated the need for effective solutions to satisfy application bandwidth and latency req...
Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, ...

Publication
163views
12 years 3 months ago
Saliency Maps of High Dynamic Range Images
A number of computational models of visual attention have been proposed based on the concept of saliency map. Some of them have been validated as predictors of the visual scan-path...
Roland Brémond, Josselin Petit and Jean-Philippe...
MSS
2000
IEEE
182views Hardware» more  MSS 2000»
13 years 12 months ago
A Blueprint for Representation Information in the OAIS Model
The CEDARS∗ project within UK academia seeks to develop a demonstrator system to recommend techniques for long-term storage of digital data primarily within the research library...
David Holdsworth, Derek M. Sergeant
ICPPW
2005
IEEE
14 years 1 months ago
Speculative Parallel Threading Architecture and Compilation
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
Xiao-Feng Li, Zhao-Hui Du, Chen Yang, Chu-Cheow Li...
SC
2000
ACM
13 years 12 months ago
Performance of Hybrid Message-Passing and Shared-Memory Parallelism for Discrete Element Modeling
The current trend in HPC hardware is towards clusters of shared-memory (SMP) compute nodes. For applications developers the major question is how best to program these SMP cluster...
D. S. Henty