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MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
14 years 4 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
SBACPAD
2008
IEEE
100views Hardware» more  SBACPAD 2008»
14 years 4 months ago
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
Jesús Alastruey, Teresa Monreal, Francisco ...
APCSAC
2007
IEEE
14 years 4 months ago
Runtime Performance Projection Model for Dynamic Power Management
In this paper, a runtime performance projection model for dynamic power management is proposed. The model is built as a first-order linear equation using a linear regression model....
Sang Jeong Lee, Hae-Kag Lee, Pen-Chung Yew
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
14 years 4 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
FSE
2007
Springer
101views Cryptology» more  FSE 2007»
14 years 4 months ago
Generalized Correlation Analysis of Vectorial Boolean Functions
We investigate the security of n-bit to m-bit vectorial Boolean functions in stream ciphers. Such stream ciphers have higher throughput than those using single-bit output Boolean f...
Claude Carlet, Khoongming Khoo, Chu-Wee Lim, Chuan...