Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...
Starting from a graphical data model (a subset of the OMT object model), a skeleton of formal specification can be generated and completed to express several constraints and provi...
We study how constraint-based static analysis can be applied to the automated and systematic debugging of program errors. Strongly moding and constraint-based mode analysis are tur...
This paper describes an architecture that begins with enough general knowledge to play any board game as a novice, and then shifts its decision-making emphasis to learned, game-sp...
In this paper, we propose a new formalism, named the Timed Communicating Finite State Machine (Timed CFSM), for specifying and verifying time-critical systems. Timed CFSM preserve...