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57
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dac 1994
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An Efficient Path Delay Fault Coverage Estimator
14 years 1 months ago
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Keerthi Heragu, Michael L. Bushnell, Vishwani D. A...
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Data Flow Partitioning for Clock Period and Latency Minimization
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Lung-Tien Liu, Minshine Shih, Chung-Kuan Cheng
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A Unified Approach to Multilayer Over-the-Cell Routing
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Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddh...
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Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-Based Designs
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Anurag P. Gupta, Daniel P. Siewiorek
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Layout Driven Logic Synthesis for FPGAs
14 years 1 months ago
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Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, ...
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