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DAC
1994
ACM
13 years 10 months ago
New Techniques for Efficient Verification with Implicitly Conjoined BDDs
-- In previous work, Hu and Dill identified a common cause of BDD-size blowup in high-level design verification and proposed the method of implicitly conjoined invariants to addres...
Alan J. Hu, Gary York, David L. Dill
DAC
1994
ACM
13 years 10 months ago
Simultaneous Placement and Module Optimization of Analog IC's
New placement techniques are presented which substantially improve the process of automatic layout generation of analog IC's. Extremely tight specifications can be enforced o...
Edoardo Charbon, Enrico Malavasi, Davide Pandini, ...
DAC
1994
ACM
13 years 10 months ago
Permissible Observability Relations in FSM Networks
Previous attempts to capture the phenomenon of output don't care sequencesfor a componentin an FSM network have been incomplete. We demonstrate that output don't care se...
Huey-Yih Wang, Robert K. Brayton
DAC
1994
ACM
13 years 10 months ago
HSIS: A BDD-Based Environment for Formal Verification
Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now...
Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin...
DAC
1994
ACM
13 years 10 months ago
Technology Mapping Using Fuzzy Logic
- This paper presents a placement-driven technology mapping procedure based on fuzzy delay curves. The fuzziness has been introduced to deal with the inherent vagueness in wiring l...
Sasan Iman, Massoud Pedram, Kamal Chaudhary