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DAC
1996
ACM
14 years 20 days ago
Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems
-- This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us ...
Eric Verlind, Gjalt G. de Jong, Bill Lin
DAC
1996
ACM
14 years 20 days ago
VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems
This paper presents a new concept for accurate modeling and timing simulationof electronicsystems integrated in a typical VHDL design environment, taking into account the requirem...
Bernhard Wunder, Gunther Lehmann, Klaus D. Mü...
DAC
1996
ACM
14 years 20 days ago
Glitch Analysis and Reduction in Register Transfer Level
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
DAC
1996
ACM
14 years 20 days ago
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures
In this paper we address the problem of code generation for basic blocks in heterogeneous memory-register DSP processors. We propose a new a technique, based on register-transfer ...
Guido Araujo, Sharad Malik, Mike Tien-Chien Lee
DAC
1996
ACM
14 years 20 days ago
Computing Parametric Yield Adaptively Using Local Linear Models
Abstract A divide-and-conquer algorithm for computing the parametric yield of large analog circuits is presented. The algorithm targets applications whose performance spreads could...
Mien Li, Linda S. Milor