In this paper, a novel automatic approach for the concurrent topology and routing optimization that achieves a high quality network layout is proposed. This optimization is based ...
Since process and environmental variations can no longer be ignored in high-performance microprocessor designs, it is necessary to develop techniques for computing the sensitiviti...
Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S...
ng Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation Yan Chen Dept. of Computer Science Portland State University Portland, OR, 97207 chenyan@cs.pdx.e...
Embedded systems with heterogeneous processors extend the energy/timing trade-off flexibility and provide the opportunity to fine tune resource utilization for particular applicat...
Michel Goraczko, Jie Liu, Dimitrios Lymberopoulos,...
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pa...