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DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
In this paper we address the problem of designing very high throughput finite state machines (FSMs). The presence of loops in sequential circuits prevents a straightforward and g...
DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
Higher levels of integration, the need for test re-use, and the mixed-signal nature of today’s SOC’s necessitate hierarchical test generation and system level test composition...
DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
The classical solving approach for two-level logic minimisation reduces the problem to a special case of unate covering and attacks the latter with a (possibly limited) branch-and...
WDAG
2000
Springer
13 years 10 months ago
2000
Springer
Work to date on algorithms for message-passing systems has explored a wide variety of types of faults, but corresponding work on shared memory systems has usually assumed that only...