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2000
IEEE
140views Hardware» more  DATE 2000»
13 years 11 months ago
Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C
-- One of the greatest challenges in C/C++-based design methodology is to efficiently map C/C++ models into hardware. Many of the networking and multimedia applications implemente...
Luc Séméria, Koichi Sato, Giovanni D...
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
13 years 11 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
DATE
2000
IEEE
130views Hardware» more  DATE 2000»
13 years 11 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
DATE
2000
IEEE
110views Hardware» more  DATE 2000»
13 years 11 months ago
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
Alper Demir, Peter Feldmann
DATE
2000
IEEE
94views Hardware» more  DATE 2000»
13 years 11 months ago
Shared Memory Implementations of Synchronous Dataflow Specifications
There has been a proliferation of block-diagram environments for specifying and prototyping DSP systems. These include tools from academia like Ptolemy [3], and GRAPE [7], and com...
Praveen K. Murthy, Shuvra S. Bhattacharyya