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2002
IEEE
105views Hardware» more  DATE 2002»
14 years 3 months ago
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
Chunhong Chen, Majid Sarrafzadeh
DATE
2002
IEEE
120views Hardware» more  DATE 2002»
14 years 3 months ago
Wire Placement for Crosstalk Energy Minimization in Address Buses
We propose a novel approach to bus energy minimization that targets crosstalk effects. Unlike previous approaches, we try to reduce energy through capacitance optimization, by ad ...
Luca Macchiarulo, Enrico Macii, Massimo Poncino
DATE
2002
IEEE
115views Hardware» more  DATE 2002»
14 years 3 months ago
Design Technology for Networked Reconfigurable FPGA Platforms
Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors tha...
Steve Guccione, Diederik Verkest, Ivo Bolsens
DATE
2002
IEEE
138views Hardware» more  DATE 2002»
14 years 3 months ago
Automatic Evaluation of the Accuracy of Fixed-Point Algorithms
The minimization of cost, power consumption and timeto-market of DSP applications requires the development of methodologies for the automatic implementation of floating-point alg...
Daniel Menard, Olivier Sentieys
DATE
2002
IEEE
87views Hardware» more  DATE 2002»
14 years 3 months ago
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods
We present a new passive model reduction algorithm based on the Laguerre expansion of the time response of interconnect networks. We derive expressions for the Laguerre coefficie...
Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok...