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78
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DATE
2003
IEEE
97views Hardware» more  DATE 2003»
15 years 11 months ago
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units
Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik...
DATE
2003
IEEE
98views Hardware» more  DATE 2003»
15 years 11 months ago
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs
Fernando Gehm Moraes, Daniel Mesquita, José...
121
Voted
DATE
2003
IEEE
100views Hardware» more  DATE 2003»
15 years 11 months ago
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals
: Binary Decision Diagrams (BDDs) have been widely used in synthesis and verification. Boolean Satisfiability (SAT) Solvers, on the other hand, have been gaining
Gianpiero Cabodi, Sergio Nocco, Stefano Quer
DATE
2003
IEEE
75views Hardware» more  DATE 2003»
15 years 11 months ago
SAT-Based Techniques in System Synthesis
In this paper, we show how to integrate SAT-based techniques into the task of system synthesis by regarding the the problems: (i) feasibility check and (ii) evaluation of quality....
Christian Haubelt, Jürgen Teich, Rainer Feldm...
132
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DATE
2003
IEEE
66views Hardware» more  DATE 2003»
15 years 11 months ago
Using RTL Statespace Information and State Encoding for Induction Based Property Checking
This paper focuses on checking safety properties for sequential circuits specified on the RT-level. We study how different state encodings can be used to create a gate-level repr...
Markus Wedler, Dominik Stoffel, Wolfgang Kunz