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DFT
2003
IEEE
13 years 12 months ago
2003
IEEE
In the last years, new requirements in terms of vehicle performance increased significantly the amount of on-board electronics, thus raising more concern about safety and fault to...
DFT
2003
IEEE
13 years 12 months ago
2003
IEEE
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
DFT
2003
IEEE
13 years 12 months ago
2003
IEEE
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
DFT
2003
IEEE
13 years 12 months ago
2003
IEEE
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtaine...
DFT
2003
IEEE
13 years 12 months ago
2003
IEEE
This paper discusses a hybrid optoelectronic scheme for a new interconnection network, "Tori connected mESHes (TESH)". The major features of TESH are the following: it i...