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DSN
2007
IEEE
14 years 1 months ago
2007
IEEE
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
DSN
2007
IEEE
13 years 10 months ago
2007
IEEE
Model-checking of asynchronous distributed protocols is challenging because of the large size of the state and solution spaces. This paper tackles this problem in the context of l...
DSN
2007
IEEE
14 years 1 months ago
2007
IEEE
As wireless hotspot business becomes a tremendous financial success, users of these networks have increasing motives to misbehave in order to obtain more bandwidth at the expense...
DSN
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we study and model a crash-recovery target and its failure detector’s probabilistic behavior. We extend Quality of Service (QoS) metrics to measure the recovery d...
DSN
2007
IEEE
14 years 1 months ago
2007
IEEE
Programmable logic arrays (PLA), which can implement arbitrary logic functions in a two-level logic form, are promising as platforms for nanoelectronic logic due to their highly r...