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ERSA
2006
133views Hardware» more  ERSA 2006»
13 years 8 months ago
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...
Cao Liang, Jing Ma, Xin-Ming Huang
SIPS
2006
IEEE
14 years 1 months ago
Configuration and Representation of Large-Scale Dataflow Graphs using the Dataflow Interchange Format
—A wide variety of DSP design tools have been developed that incorporate dataflow graph representations into their GUI-based design environments. However, as the complexity of ap...
Ivan Corretjer, Chia-Jui Hsu, Shuvra S. Bhattachar...
CDES
2006
240views Hardware» more  CDES 2006»
13 years 8 months ago
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
Arun N. Chandorkar, Gurvinder Singh
ASC
2004
13 years 7 months ago
Efficient fuzzy compiler for SIMD architectures
Abstract. This paper presents a real-time full-programmable fuzzy compiler based on piecewise linear interpolation techniques designed to be executed in SIMD (Single Instruction Mu...
Enrique Frías-Martínez, Julio Guti&e...
ICMCS
2006
IEEE
136views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Architecture Analysis for Low-Delay Video Coding
Low-delay video coding is a key technology for video conferencing as well as upcoming remote-monitoring and automotive video applications like rear-view cameras or night vision sy...
Ralf M. Schreier, A. Tushar Iqbal Rahman, Ganesh K...