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ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
14 years 1 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
12 years 10 months ago
Soft error benchmarking of L2 caches with PARMA
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram,...
ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
13 years 11 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
HIPEAC
2011
Springer
12 years 7 months ago
Decoupled zero-compressed memory
For each computer system generation, there are always applications or workloads for which the main memory size is the major limitation. On the other hand, in many cases, one could...
Julien Dusser, André Seznec
ESA
2001
Springer
75views Algorithms» more  ESA 2001»
14 years 23 hour ago
Strongly Competitive Algorithms for Caching with Pipelined Prefetching
Suppose that a program makes a sequence of m accesses (references) to data blocks, the cache can hold k < m blocks, an access to a block in the cache incurs one time unit, and ...
Alexander Gaysinsky, Alon Itai, Hadas Shachnai