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CCGRID
2003
IEEE
15 years 8 months ago
Discretionary Caching for I/O on Clusters
I/O bottlenecks are already a problem in many largescale applications that manipulate huge datasets. This problem is expected to get worse as applications get larger, and the I/O ...
Murali Vilayannur, Anand Sivasubramaniam, Mahmut T...
EUROPAR
2009
Springer
15 years 7 months ago
Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs
In response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latenci...
Javier Lira, Carlos Molina, Antonio Gonzále...
ICS
1999
Tsinghua U.
15 years 7 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer
ASPLOS
1998
ACM
15 years 7 months ago
Cache-Conscious Data Placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Brad Calder, Chandra Krintz, Simmi John, Todd M. A...
131
Voted
DAC
2008
ACM
16 years 4 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov