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JEA
2006
83views more  JEA 2006»
13 years 7 months ago
Cache-Friendly implementations of transitive closure
In this paper we show cache-friendly implementations of the Floyd-Warshall algorithm for the All-Pairs ShortestPath problem. We first compare the best commercial compiler optimiza...
Michael Penner, Viktor K. Prasanna
ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
13 years 5 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
MICRO
1998
IEEE
128views Hardware» more  MICRO 1998»
13 years 12 months ago
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors
The fill unit is the structure which collects blocks of instructions and combines them into multi-block segments for storage in a trace cache. In this paper, we expand the role of...
Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
FPL
2009
Springer
130views Hardware» more  FPL 2009»
14 years 7 days ago
Tracking elephant flows in internet backbone traffic with an FPGA-based cache
This paper presents an FPGA-friendly approach to tracking elephant flows in network traffic. Our approach, Single Step Segmented Least Recently Used (S3 -LRU) policy, is a netwo...
Martin Zádník, Marco Canini, Andrew ...
IPPS
2000
IEEE
13 years 12 months ago
Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
Jim Nilsson, Fredrik Dahlgren