Rank-aware cache replacement and write buffering to improve DRAM energy efficiency

DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips reduces power consumption but comes at a performance penalty to return to full power for servicing requests. We propose a novel cache replacement policy and write buffer that prevents cache blocks going to certain DRAM chips from being replaced, resulting in less requests going to these chips, and allowing them to remain idle for longer periods of time. Our proposed modifications improve DRAM energy efficiency by 10% on average (up to 30%) compared to a base case that utilizes low power modes, and by 76% compared to a base case that does not utilize power saving modes. Categories and Subject Descriptors C.0 [Computer Systems Organization]: System architectures General Terms: Design, Performance

• Type: Journal
• Year: 2010
• Where: ISLPED
• Authors: Ahmed M. Amin, Zeshan Chishti
• Keywords: DRAM, DRAM Chips, Energy Efficiency, Hardware, ISLPED 2010