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ISCA
2012
IEEE
302views Hardware» more  ISCA 2012»
11 years 10 months ago
Scale-out processors
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, ...
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
13 years 12 months ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi
JPDC
2007
60views more  JPDC 2007»
13 years 7 months ago
The impact of wrong-path memory references in cache-coherent multiprocessor systems
The core of current-generation high-performance multiprocessor systems is out-of-order execution processors with aggressive branch prediction. Despite their relatively high branch...
Resit Sendag, Ayse Yilmazer, Joshua J. Yi, Augustu...
USENIX
1994
13 years 9 months ago
A Better Update Policy
y-filled data block results in a delayed write,Abstract while a modification that fills a block results in an immediate, although asynchronous, write. TheSome file systems can dela...
Jeffrey C. Mogul
ASPDAC
2006
ACM
126views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A novel instruction scratchpad memory optimization method based on concomitance metric
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performance of certain embedded systems. Additionally, it has also been demonstrated tha...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...