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IPPS
2010
IEEE
13 years 5 months ago
A lock-free, cache-efficient multi-core synchronization mechanism for line-rate network traffic monitoring
Line-rate data traffic monitoring in high-speed networks is essential for network management. To satisfy the line-rate requirement, one can leverage multi-core architectures to par...
Patrick P. C. Lee, Tian Bu, Girish P. Chandranmeno...
IPPS
2008
IEEE
14 years 1 months ago
LiteLoad: Content unaware routing for localizing P2P protocols
In today’s extensive worldwide Internet traffic, some 60% of network congestion is caused by Peer to Peer sessions. Consequently ISPs are facing many challenges like: paying fo...
Shay Horovitz, Danny Dolev
CF
2008
ACM
13 years 9 months ago
A modular 3d processor for flexible product design and technology migration
The current methodology used in mass-market processor design is to create a single base microarchitecture (e.g., Intel's "Core"or AMD's"K8") that is ...
Gabriel H. Loh
ASPLOS
2006
ACM
13 years 9 months ago
Tradeoffs in fine-grained heap memory protection
Different uses of memory protection schemes have different needs in terms of granularity. For example, heap security can benefit from chunk separation (by using protected "pa...
Jianli Shen, Guru Venkataramani, Milos Prvulovic
SYSTOR
2009
ACM
14 years 2 months ago
DHIS: discriminating hierarchical storage
A typical storage hierarchy comprises of components with varying performance and cost characteristics, providing multiple options for data placement. We propose and evaluate a hie...
Chaitanya Yalamanchili, Kiron Vijayasankar, Erez Z...