The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have develop...
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...
With the growing needs of information sharing and exchange, MHEG-6(Multimedia Hypermedia information coding Expert Group - part 6) standard is defined so as to provide the interna...
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...
Several studies have demonstrated that out-of-order execution processors may not be the most adequate organization for wide issue processors due to the increasing penalties that w...
This paper suggests a new image compression scheme, using the discrete wavelet transformation (DWT), which is based on attempting to preserve the texturally important image charac...
Dimitris A. Karras, S. A. Karkanis, Basil G. Mertz...