This paper describes the package of test bench code required to verify the Algotronix' AES IP Core. Several authors (see the references in [3]) have published papers detailing...
In this paper we present a method for FPGA datapath precision optimization subject to user-defined area and error constraints. This work builds upon our previous research [1] which...
In this paper we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We...
We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision ReedSolomon decoding algorithm. The key feature is the embedding of b...
Warren J. Gross, Frank R. Kschischang, P. Glenn Gu...
In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). Current software-based NIDS are too compute intensive and can not ...