Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
Run-time assignment of a set of communicating tasks onto a heterogeneous multiprocessor system-on-chip (MPSoC) platform is a challenging task. Having FPGA fabric tiles in such MPS...
Vincent Nollet, Prabhat Avasare, Diederik Verkest,...
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...
FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle pr...
In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The pr...