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ERSA
2006
100views Hardware» more  ERSA 2006»
13 years 10 months ago
Relocation and Defragmentation for Heterogeneous Reconfigurable Systems
Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
Markus Koester, Heiko Kalte, Mario Porrmann
ERSA
2006
119views Hardware» more  ERSA 2006»
13 years 10 months ago
Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment
Run-time assignment of a set of communicating tasks onto a heterogeneous multiprocessor system-on-chip (MPSoC) platform is a challenging task. Having FPGA fabric tiles in such MPS...
Vincent Nollet, Prabhat Avasare, Diederik Verkest,...
FPGA
2006
ACM
195views FPGA» more  FPGA 2006»
14 years 8 days ago
An adaptive Reed-Solomon errors-and-erasures decoder
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...
MAM
2006
95views more  MAM 2006»
13 years 8 months ago
Stochastic spatial routing for reconfigurable networks
FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle pr...
André DeHon, Randy Huang, John Wawrzynek
ASAP
2006
IEEE
121views Hardware» more  ASAP 2006»
14 years 10 days ago
Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit
In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The pr...
Humberto Calderon, Stamatis Vassiliadis