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FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
14 years 2 months ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
GLOBECOM
2006
IEEE
14 years 2 months ago
Protograph LDPC Codes with Node Degrees at Least 3
— In this paper we present protograph codes with a small number of degree-3 nodes and one high degree node. The iterative decoding threshold for proposed rate 1/2 codes are lower...
Dariush Divsalar, Christopher Jones
INFOCOM
2006
IEEE
14 years 2 months ago
Reverse Hashing for High-Speed Network Monitoring: Algorithms, Evaluation, and Applications
— A key function for network traffic monitoring and analysis is the ability to perform aggregate queries over multiple data streams. Change detection is an important primitive w...
Robert T. Schweller, Zhichun Li, Yan Chen, Yan Gao...
IPPS
2006
IEEE
14 years 2 months ago
MegaProto/E: power-aware high-performance cluster with commodity technology
In our research project named “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, we have been developing a prototype cluster not based on ASIC or FPGA...
Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, H...
IPPS
2006
IEEE
14 years 2 months ago
Exploiting processing locality through paging configurations in multitasked reconfigurable systems
FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of ...
T. Taher, Tarek A. El-Ghazawi