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FPL
2009
Springer
79views Hardware» more  FPL 2009»
14 years 2 days ago
A reconfigurable architecture for the Phylogenetic Likelihood Function
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run effici...
Nikolaos Alachiotis, Alexandros Stamatakis, Euripi...
FPL
2009
Springer
145views Hardware» more  FPL 2009»
14 years 2 days ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...
FPL
2009
Springer
96views Hardware» more  FPL 2009»
14 years 2 days ago
Noise impact of single-event upsets on an FPGA-based digital filter
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets ...
Brian H. Pratt, Michael J. Wirthlin, Michael P. Ca...
FPL
2009
Springer
135views Hardware» more  FPL 2009»
14 years 2 days ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
Martin Labrecque, J. Gregory Steffan
ERSA
2009
149views Hardware» more  ERSA 2009»
13 years 5 months ago
Hardware-Optimized Ziggurat Algorithm for High-Speed Gaussian Random Number Generators
Many scientific and engineering applications, which are increasingly being ported from software to reconfigurable platforms, require Gaussian-distributed random numbers. Thus, the...
Hassan Edrees, Brian Cheung, McCullen Sandora, Dav...