Run-time Partial Reconfiguration speed investigation and architectural design space exploration

Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Access (DMA), Master (MST) burst, and a dedicated Block RAM (BRAM) cache respectively to reduce the reconfiguration time. Based on the Xilinx PR technology and the Internal Configuration Access Port (ICAP) primitive in the FPGA fabric, we discuss multiple design architectures and thoroughly investigate their performance with measurements for different partial bitstream sizes. Compared to the reference OPB HWICAP and XPS HWICAP designs, experimental results show that DMA HWICAP and MST HWICAP reduce the reconfiguration time by one order of magnitude, with little resource consumption overhead. The BRAM HWICAP design can even approach the reconfiguration speed limit of the ICAP primitive at the cost of large Block RAM utilization.

• Type: Conference
• Year: 2009
• Where: FPL
• Authors: Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch
• Keywords: Block RAM, FPL 2009, Hardware, Hwicap Design, Reconfiguration Time