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FPL
2004
Springer
87views Hardware» more  FPL 2004»
14 years 1 months ago
Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs
This paper presents an innovative way to deploy Bitstream Intellectual Property (BIP) cores. By using standard tools to generate bitstreams for Field Programmable Gate Arrays (FPGA...
Edson L. Horta, John W. Lockwood
FPL
2004
Springer
141views Hardware» more  FPL 2004»
14 years 1 months ago
Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs
—This paper presents a methodology and a tool for automatic synthesis of highly efficient intrusion detection systems using a high-level, graph-based partitioning methodology and...
Zachary K. Baker, Viktor K. Prasanna
FPL
2004
Springer
122views Hardware» more  FPL 2004»
14 years 1 months ago
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path
A high-performance reconfigurable coarse-grain data-path, part of a hybrid reconfigurable platform, is introduced. The data-path consists of coarse grain components that their flex...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
FPL
2004
Springer
83views Hardware» more  FPL 2004»
14 years 1 months ago
System-Level Modeling of Dynamically Reconfigurable Co-processors
Dynamically reconfigurable co-processors (DRCs) are interesting design alternatives when both flexibility and performance are concerns. However, it is difficult to study the perfor...
Yang Qu, Kari Tiensyrjä, Kostas Masselos
FPL
2004
Springer
74views Hardware» more  FPL 2004»
14 years 1 months ago
Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers
The paper describes two methods for the design of matrix-oriented SAT solvers based on data compression. The first one provides matrix compression in a host computer and decompress...
Valery Sklyarov, Iouliia Skliarova, Bruno Figueire...