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FPL
2007
Springer
120views Hardware» more  FPL 2007»
14 years 4 months ago
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays
In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameter...
Yohei Hasegawa, Hideharu Amano
FPL
2007
Springer
141views Hardware» more  FPL 2007»
14 years 4 months ago
Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration
The effect of kernel operations on cache optimisations in a soft-core reconfigurable system is important for dynamic cache switching design. Considering kernel operations changes ...
John Shield, Peter Sutton, Philip Machanick
FPL
2007
Springer
136views Hardware» more  FPL 2007»
14 years 4 months ago
A Load/Store Unit for a Memcpy Hardware Accelerator
Recently, a dedicated hardware accelerator was proposed that works in conjunction with caches found next to modern-day microprocessors, to speedup the commonly utilized memcpy ope...
Stamatis Vassiliadis, Filipa Duarte, Stephan Wong
FPL
2007
Springer
126views Hardware» more  FPL 2007»
14 years 4 months ago
A Time-Triggered Network-on-Chip
In this paper we propose a time-triggered network-onchip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature...
Martin Schoeberl
FPL
2007
Springer
154views Hardware» more  FPL 2007»
14 years 4 months ago
Physical Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection
In recent years, IP protection of FPGA hardware designs has become a requirement for many IP vendors. To this end solutions have been proposed based on the idea of bitstream encry...
Jorge Guajardo, Sandeep Kumar, Geert Jan Schrijen,...