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GLVLSI
2000
IEEE
69views VLSI» more  GLVLSI 2000»
14 years 3 months ago
Supporting system-level power exploration for DSP applications
System-level power exploration requires tools for estimation of the overall power consumed by a system, as well as a detailed breakdown of the consumption of its main functional b...
Luca Benini, Marco Ferrero, Alberto Macii, Enrico ...
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
14 years 3 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
GLVLSI
2000
IEEE
85views VLSI» more  GLVLSI 2000»
14 years 3 months ago
Fast and accurate estimation of floorplans in logic/high-level synthesis
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
GLVLSI
2000
IEEE
113views VLSI» more  GLVLSI 2000»
14 years 3 months ago
A novel technique for sea of gates global routing
We present a novel global routing and cross-point assignment methodology for sea-of-gates (SOG) designs. Using the proposed congestion driven spanning trees (CDST), and continuous...
Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
14 years 3 months ago
CMOS system-on-a-chip voltage scaling beyond 50nm
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoo...