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TCAD
2008
75views more  TCAD 2008»
13 years 7 months ago
An Efficient Graph-Based Algorithm for ESD Current Path Analysis
Abstract--The electrostatic discharge (ESD) problem has become a challenging reliability issue in nanometer-circuit design. High voltages that resulted from ESD might cause high cu...
Chih-Hung Liu, Hung-Yi Liu, Chung-Wei Lin, Szu-Jui...
JETC
2008
127views more  JETC 2008»
13 years 6 months ago
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
Yong Zhan, Sachin S. Sapatnekar
FUIN
2008
101views more  FUIN 2008»
13 years 7 months ago
Translation of Intermediate Language to Timed Automata with Discrete Data
The aim of this work is to describe the translation from Intermediate Language, one of the input formalisms of the model checking platform VerICS, to timed automata with discrete d...
Agata Janowska, Pawel Janowski, Dobieslaw Wr&oacut...
ASPDAC
2008
ACM
107views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Full-chip thermal analysis for the early design stage via generalized integral transforms
The capability of predicting the temperature profile is critically important for timing estimation, leakage reduction, power estimation, hotspot avoidance and reliability concerns ...
Pei-Yu Huang, Chih-Kang Lin, Yu-Min Lee
ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
14 years 4 months ago
Test-access mechanism optimization for core-based three-dimensional SOCs
— Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Su...
Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yua...