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ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
- This paper presents a non-scan design-for-testability technique applicable to register-transfer(RT) level data path circuits, which are usually very hard-to-test due to the prese...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
We give the rst single-layer clock tree construction with exact zero skew according to the Elmore delay model. The previous Linear-Planar-DME method 11 guarantees a planar solutio...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
The reuse of well-tested and optimized design objects is an important aspect for decreasing design times, increasing design quality, and improving the predictability of designs. R...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
Interconnectperformance does not scale well into deep submicron dimensions, and the rising number of analog effects erodes tal abstraction necessary for high levels of integration...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
? We describe a synthesis system that takes operating range constraints and inter- and intra- circuit parametric manufacturing variations into account while designing a sized and b...