— This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel ...
Altan Odabasioglu, Mustafa Celik, Lawrence T. Pile...
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational ...
With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In...
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
This paper presents the underlying methodology of Cosmos, an interactive approach for hardware software co-design capable of handling multiprocessor systems and distributed archit...