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ICCAD
2001
IEEE
102views Hardware» more  ICCAD 2001»
14 years 6 months ago
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...
ICCAD
2001
IEEE
106views Hardware» more  ICCAD 2001»
14 years 6 months ago
Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation
- This paper presents a spectrally-weighted balanced truncation technique for RLC interconnects, a technique needed when the interconnect circuit parameters change as a result of v...
Payam Heydari, Massoud Pedram
ICCAD
2001
IEEE
152views Hardware» more  ICCAD 2001»
14 years 6 months ago
Hybrid Structured Clock Network Construction
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
Haihua Su, Sachin S. Sapatnekar
ICCAD
2001
IEEE
184views Hardware» more  ICCAD 2001»
14 years 6 months ago
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
Cagdas Akturan, Margarida F. Jacome
ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
14 years 6 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...