The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). State-of-the-art methods use simulat...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Ha...
Faster-than-at-speed test have been proposed to detect small delay defects. While these techniques increase the test frequency to reduce the positive slack of the path, they exace...
Recent successful techniques for the efficient simulation of largescale interconnect models rely on the sparsification of the inverse of the inductance matrix L. While there are...
Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Ko...
Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction....