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ICCAD
2007
IEEE
134views Hardware» more  ICCAD 2007»
14 years 7 months ago
Hybrid CEGAR: combining variable hiding and predicate abstraction
ion Chao Wang NEC Laboratories America Hyondeuk Kim University of Colorado Aarti Gupta NEC Laboratories America Variable hiding and predicate abstraction are two popular abstracti...
Chao Wang, Hyondeuk Kim, Aarti Gupta
ICCAD
2007
IEEE
105views Hardware» more  ICCAD 2007»
14 years 5 months ago
Victim alignment in crosstalk aware timing analysis
Modeling the effect of coupling noise on circuit delay is a key issue in static timing analysis (STA) and involves the “victimaggressor alignment” problem. As delay-noise depe...
Ravikishore Gandikota, Kaviraj Chopra, David Blaau...
ICCAD
2007
IEEE
113views Hardware» more  ICCAD 2007»
14 years 5 months ago
The FAST methodology for high-speed SoC/computer simulation
— This paper describes the FAST methodology that enables a single FPGA to accelerate the performance of cycle-accurate computer system simulators modeling modern, realistic SoCs,...
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Pa...
ICCAD
2007
IEEE
151views Hardware» more  ICCAD 2007»
14 years 2 months ago
A design flow dedicated to multi-mode architectures for DSP applications
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...
Cyrille Chavet, Caaliph Andriamisaina, Philippe Co...
ICCAD
2007
IEEE
165views Hardware» more  ICCAD 2007»
14 years 2 months ago
Automated refinement checking of concurrent systems
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for...
Sudipta Kundu, Sorin Lerner, Rajesh Gupta