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ICCD
2000
IEEE
103views Hardware» more  ICCD 2000»
14 years 4 months ago
Efficient Place and Route for Pipeline Reconfigurable Architectures
In this paper, we present a fast and eficient compilation methodology for pipeline reconfigurable architectures. Our compiler back-end is much faster than conventional CAD tools, ...
Srihari Cadambi, Seth Copen Goldstein
ICCD
2000
IEEE
124views Hardware» more  ICCD 2000»
14 years 4 months ago
Processors for Mobile Applications
: Mobile processors form a large and very fast growing segment of semiconductor market. Although they are used in a great variety of embedded systems such as personal digital organ...
Farinaz Koushanfar, Miodrag Potkonjak, Vandana Pra...
ICCD
2000
IEEE
94views Hardware» more  ICCD 2000»
14 years 7 hour ago
Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies
In system-on-a-chip design, interfacing of Intellectual Property(IP) blocks is one of the most important issues. Since most IP’s are provided by different vendors, they have dif...
Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min ...
ICCD
2000
IEEE
69views Hardware» more  ICCD 2000»
14 years 7 hour ago
Hierarchical Simulation of a Multiprocessor Architecture
When proposing new architectural enhancements, it is also important to account for the hardware complexity. To achieve this goal, we propose to model the new design in a hardware ...
Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra
ICCD
2004
IEEE
87views Hardware» more  ICCD 2004»
14 years 4 months ago
Evaluating Techniques for Exploiting Instruction Slack
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efï¬...
Yau Chin, John Sheu, David Brooks