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ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
14 years 7 months ago
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor
In this work we propose a methodology for the accurate analysis of the power consumption of interprocessor communication in a MPSoC, and the construction of high-level power macro...
Mirko Loghi, Luca Benini, Massimo Poncino
ICCD
2004
IEEE
111views Hardware» more  ICCD 2004»
14 years 7 months ago
Potential Slack Budgeting with Clock Skew Optimization
Potential slack is an effective metric of circuit’s possible performance improvement. It is equal to the maximal amount of slack that can be potentially used for optimization. I...
Kai Wang, Malgorzata Marek-Sadowska
ICCD
2004
IEEE
98views Hardware» more  ICCD 2004»
14 years 7 months ago
Coping with The Variability of Combinational Logic Delays
Abstract— This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on du...
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno...
ICCD
2004
IEEE
122views Hardware» more  ICCD 2004»
14 years 7 months ago
Quality Improvement Methods for System-Level Stimuli Generation
Functional verification of systems is aimed at validating the integration of previously verified components. It deals with complex designs, and invariably suffers from scarce re...
Roy Emek, Itai Jaeger, Yoav Katz, Yehuda Naveh
ICCD
2004
IEEE
112views Hardware» more  ICCD 2004»
14 years 7 months ago
An Infrastructure IP for On-Chip Clock Jitter Measurement
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
Jui-Jer Huang, Jiun-Lang Huang