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ICCD
2005
IEEE
14 years 7 months ago
2005
IEEE
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
ICCD
2005
IEEE
14 years 7 months ago
2005
IEEE
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access l...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
— In this work we investigate the buffer insertion problem under process variations. Sub 100-nm fabrication process causes significant variations on many design parameters. We p...
ICCD
2005
IEEE
14 years 7 months ago
2005
IEEE
Traditional approaches for sequential logic optimization include (1) explicit state-based techniques such as state minimization, (2) structural techniques such as retiming, and (3...
ICCD
2005
IEEE
14 years 7 months ago
2005
IEEE
The advent of nanometer feature sizes in silicon fabrication has triggered a number of new design challenges for computer designers. These challenges include design complexity and...