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ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
As the VLSI technology marches beyond 65 and 45nm process technologies, variation in gate length has a direct impact on leakage and performance of CMOS transistors. Due to sub-wav...
ICCD
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
ICCD
2007
IEEE
13 years 11 months ago
2007
IEEE
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper presents the Finished Store Buffer (or FSB), an alternative and position-insensitive approach for building a scalable store buffer for an out-of-order processor. Exploi...