–This paper provides proof of concept for the newly-approved 1149.6 standard by investigating the first silicon implementation of the test receiver. EXTEST and EXTEST_PULSE tests...
Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by...
Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains Pradiptya Ghosh, Chung-shin Kang, Michael Sanie and David Pinto Numerical Technologies, 70 West P...
Pradiptya Ghosh, Chung-shin Kang, Michael Sanie, D...
An intermediate solution between conventional printed circuit board technology and wafer level packaging, WLP, is to fabricate interconnection circuits and flip chip assembly stru...
Today’s low cost wireless phones have driven a need to be able to economically test high volumes of complex RF IC’s at a fraction of the cost of the IC. In June of 2001 the IB...